1. Field of the Invention
The present invention relates to a pipeline circuit with a test circuit and an automatic test pattern generating method for testing the same, and particularly to a pipeline circuit with a test circuit with small circuit scale and an automatic test pattern generating method for testing the same.
2. Description of the Background Art
Test Pattern generation for pipeline circuit generally employs engineering work station.
The pipeline circuit in the present specification includes groups of flipflops (FFs) at n stages arranged in series, and combinational circuits located between the groups of FFs at the respective stages. A combinational circuit located between the group of FFs at the i-th stage and the group of FFs at the (i+1)th stage receives an output from the group of FFs at the i-th stage, performs a predetermined logical operation on the output and then input its output value to the group of FFs at the (i+1)th stage.
Referring to FIG. 1 a pipeline circuit 220 includes: a group of FFs 60A at a first stage; a combinational circuit 62A for receiving a value held by the group of FFs 60A and performing a predetermined logical operation thereon; a group of FFs 60B at a second stage for receiving the operation result of combinational circuit 62A and holding the value; a combinational circuit 62B for receiving the value held by the group of FFs 60B and performing a predetermined logical operation thereon; a group of FFs 60C at a third stage for receiving the operation result of combinational circuit 62B and holding the value; a combinational circuit 62C for receiving the value held by the group of FFs 60C and performing a predetermined logical operation thereon; a group of FFs 60D at a fourth stage for receiving the operation result of combinational circuit 62C and holding the value; a combinational circuit 62D for receiving the value held by the group of FFs 60D and performing a predetermined logical operation thereon; and a group of FFs 60E at a fifth stage for receiving the operation result of combinational circuit 62D and holding the value.
The pipeline circuit 220 thus configured is often used in the large scale integration (LSI) for operation processing so as to implement rapid processing using transistors with limited processing performance. However, LSI, incapable of direct circuit inspection, requires consideration to the method of testing it, and scan test is considered as one technique for the method. A method of a universal, automatic test pattern generation (ATPG) for scan test for pipeline circuit 220 includes full scan ATPG and partial scan ATPG.
All of the FFs configuring pipeline circuit 220 are subjected to scan conversion to provide the FIG. 2 pipeline circuit 222 which also includes scan chain 93 interconnecting each of the groups of FFs 60A-60E. Pipeline circuit 222 thus subjected to scan conversion allows the operator to provide shift operation via scan chain 93. Thus, the operator can readily set a value of a scan FF (i.e. a FF subjected to scan conversion) via a scan-in terminal 65 and observe it via a scan-out terminal 67.
A processing procedure of full scan ATPG will now be described with reference to FIG. 3. Combinational circuits 62A-62D are extracted from pipeline circuit 222 after scan conversion (S32). An ATPG according to a predetermined method is applied for each of combinational circuits 62A-62D extracted at S32 (S34). Test patterns generated in the processing at S34 are those for combinational circuits 62A-62D and cannot be used for scan test as they are. Accordingly, the test patterns are formatted to provide test patterns for scan test (S36). For example, a test pattern for combinational circuit 62A prior to the formatting represents a relation between an input value and an output value of combinational circuit 62A. In scan test, the input value successively shifts while it is read via scan-in terminal 65, to set a value input to each FF of the group of FFs 60A. Then, a capture clock is applied one time to combinational circuit 62A and an output value is received by each FF of the group of FFs 60B. Then, a shift operation is provided a predetermined number of times and the output value of combinational circuit 62A is observed from scan-out terminal 67. To allow such a scan test, the processing at S36 provides a predetermined formatting for test patterns.
Thus, full scan ATPG can generate a test pattern which ensures testing all combinational circuits. The test pattern is also compact and provides wide fault detection coverage.
A processing procedure of partial scan ATPG will now be described with reference to FIGS. 4 and 5. Pipeline circuit 220 is analyzed and the FFs are arranged in the order of poor controllability/observability (S42). The number of FFs subjected to scan conversion (i.e. the total number of FFs in the circuit multiplied by a given scan rate) is calculated and the FFs are subjected to scan conversion in the order of poor controllability/observability (S44). Referring to FIG. 5, the scan conversion results in a pipeline circuit 224 as one example.
The controllability of a FF is determined depending on whether the data of the FF can readily be set as desired by the user only via an input port external to the LSI. For example, among the FFs configuring a multibit counter, the FF corresponding to the most significant bit of a counter value is considered as having poor controllability, since changing the value of the FF requires a great number of clocks to be applied to the multibit counter. It should be noted, however, that the controllability of a FF is determined relatively and varies depending on the peripheral circuitry.
The observability of a FF is determined depending on whether the value of the FF can readily be observed via an output port (not shown) of the LSI. For example, a long logical pass provided between a FF and the output port that also includes a large number of FFs thereon makes it difficult to transmit the value of the FF to the output port and thus generally results in a poor observability of the FF.
An ATPG is performed for a sequential circuit for conducting a scan test via a scan path 95 of pipeline circuit 224 (S46). Finally, a test pattern, is formatted, as in the processing of full scan ATPG (S48).
The processing of full scan ATPG described above can ensure testing all of combinational circuits and generate a compact test pattern with wide fault detection coverage. However, the FFs included in a pipeline circuit all require scan conversion and the scan FFs result in increasing the scale of the test circuit.
By contrast, the processing of partial scan ATPG does not require all of the FFs to be subjected to scan conversion. Accordingly, low scan rate can be set to reduce the scale of the test circuit. However, it is generally difficult to provide the ATPG processing for the sequential circuit. Also, the lowered scan rate disadvantageously decreases the rate of failure detection and results in enormous test pattern. Furthermore, since test pattern generation is provided taking into consideration the state of the sequential circuit, pipeline circuit 224 need be generally processed as a whole. However, the current performance of engineering work station cannot allow for circuits of large scale.